Semiconductor Engineering

A Primer On Last-Level Cache Memory For SoC Designs

System-on-chip (SoC) architects have a new memory technology, last level cache (LLC), to help overcome the design obstacles of bandwidth, latency and power consumption in megachips for advanced driver ...
Semiconductor Engineering

How Memory Design Optimizes System Performance

Exponential increases in data and demand for improved performance to process that data has spawned a variety of new approaches to processor design and packaging, but it also is driving big changes on ...
Electronic Design

Hardware Compression Works at the Memory Cache Level

How lossless data compression can reduce memory and power requirements. How ZeroPoint’s compression technology differs from the competition. One can never have enough memory, and one way to get more ...
TechRepublic

Design of Cache Memory with Cache Controller Using VHDL

The authors report on the design of efficient cache controller suitable for use in FPGA-based processors. Semiconductor memory which can operate at speeds comparable with the operation of the ...
Electronic Design

CXL Switch SoC Unlocks More Memory for AI

Check out our coverage of the 2023 Flash Memory Summit. This article is also part of the TechXchange: CXL for Memory and More. PCI Express (PCIe) is the de facto standard peripheral interface. Running ...
Forbes

Memory At The 2023 Designcon

The 2023 Designcon at the Santa Clara Convention Center covered lots of topics related to semiconductor design and electronics Integration. This included a session that I moderated. In addition, ...