EDN

How to raise the RTL abstraction level and design conciseness with SystemVerilog – Part 1

With the advent of advanced HDLs – such as SystemVerilog – that provide new and powerful language constructs, current hardware modeling styles can now be enhanced both in terms of abstraction level ...
EDN

Next-generation Verilog rises to higher abstraction levels

SAN JOSE, Calif. — A radically revised Verilog language took shape at the International HDL Conference here, as presenters unveiled a language reaching toward much higher levels of abstraction.